Cyclone IV Gbps pure serializer design

I am looking for a reference design or relevant IP primitives to define a pure serializer that will play back cyclically a set of 128 to 256 bits stored in the on chip memory at the top speed of 2.5Gbps. (Using the DK-START-4CGX15N board)

I defined the half rate pll in Qsts and am looking for the components which can construct the serializer. I am having trouble finding the relevant primitives. (I was thinking of constructing a MUX with the requisite number of inputs that will serialize the data - but I know that the core logic cannot drive the output data rate in a single wire - Do I need to work with a tired serializer? Is there a high speed stage that can drive the Gxb pin?