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Altera_Forum
Honored Contributor
10 years agoDoes nCONFIG get held low by the FPGA during POR?
I have two banks (Banks 2 and 5) powered at 2.5V for a LVDS interfaces and the rest powered at 3.3V for CMOS interfaces, could this be playing havoc with the POR? Checking the 1.2V core and 2.5V rails now to see if there is a problem with them. We have been able to run several of the boards in house down below -40C and get 100% start-up, the customer's sees problems below -20C. We are using the customer's host in our in house tests and so far have not been able to duplicate the problem. I've run out of straws to grasp at, any more suggestions?