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Altera_Forum
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7 years ago

Cyclone IV E Speed Grad and Design Issues

Hallo We have a test hardware with the DE0 NANO Board which has the FPGA EP4CE22F17C6. The target Fmax for our design is 50 MHz and it can be achived in the FPGA thats on the DE0 NANO board wit...
Altera_Forum's avatar
Altera_Forum
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7 years ago

I dont have a test bench in general, but i can generate validation model from MATLAB, which is the same model in Simulink as VHDL code with all the pipeline registers and other HDL coder optimizations. I compare it there. Can you please tell me how to check if my data flow is correctly synchronized???

Would adding a PLL help? although at this moment i have no idea how to add a PLL to a simulink design