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Yes exactly. You can start by looking for the longest combinatorial paths reported by timequest and see if you can change the code there, or add some pipelining.
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That's what i have done, i have identified the problematic paths. Adding pipeline registers solve the problem with Fmax but the problem is it somehow destroys the final output. We have a custom made noise shape block at the output and that needs a lot of calculation thats what making it slower, adding pipeline introduces delay blocks in the end, which is making the final output go wrong. We need to find a way to change our design to fit the timing.
I am using Simulink and MATLAB HDL coder to generate the VHDL code and then i compile it in Quartus.
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