Hallo Everybody, I would like you guys to suggest a solution for the problem below: I have successfully updated the hardware and software configurations of my project on the EPCS device and have tested the device by resetting it. Everything works perfectly. Now I did my experiments with the Nios II flash programmer. And there were no problems. now considering a situation where a connection through the jtag interface is not available, i would like to perform the update also through a fieldbus or ethernet. i have already read up on preparing the configuration files to be written to the flash (elf2flash, sof2flash). i can also transfer the files and store it in the flash memory. now my question is, if i am using the default epcs boot copier, do i write the fpga configuration first and then the software application, one after the other on to the flash?? or is there a specific rule, how i store these files on to the flash memory? If there are any other posts or documentation that I can read with respect to this issue, please let me know. Thank you very much Cheers kaushik.

Have you already read AN521 ? Moreover, if you search the forum for "remote update" you'll find a lot of threads on this subject. For example this one: http://www.alteraforum.com/forum/showthread.php?t=20623

Thank you very much for the reply. I have read the AN521 already and from your post I have read the related topics from other posts. I have achieved in successfully copying the required firmware files on to the Flash device. But now when I reset it it would not start. And I am guessing it has something to do with the Bootloader. I would like to first use the default bootloaders from Altera. the question is where should i specify which bootloader i would be using. should i be integrating the bootloader in to the sof or the elf file or should i copy it reperately to the epcs on-chip rom.

The bootloader is part of the EPCS controller integrated in the SOPC/QSys system. Just point the Nios CPU's reset vector to the EPCS controller and the bootloader will load the .elf file from the flash. The bootloader will jump over the .sof image, so the .elf just needs to be placed after the FPGA image in the flash. What file format are you using when you send data to your application, and how do you write it to the EPCS? The easiest format is probably .rbf, but IIRC with the EPCS flash you need to revert the bit order of every byte before you write them.

The bootloader is encapsulated in the fpga configuration, namely in the sof file. When you add a epcs controller, the default bootloader is automatically added to the project and built in fpga configuration. You should have a epcs_controller_boot_rom.hex in your Quartus project directory; if I recall correctly this is the default name associated to epcs, but you can change it in Quartus settings or in Qsys. If you need a custom bootloader you simply change the file and rebuild fpga. When you regenerate the Qsys component including epcs controller, the hex file is automatically overwritten with the default one. So you must pay attention to replace it with the custom version whenever you change anything in Qsys.

Thank you for the reply. Regarding my firmware files, here is how I prepare them: 1. I use the Nios II Command shell, to generate the hardware and software firmware files using sof2flash and elf2flash. 2. Then I comvert them in to the .bin files. 3. Finally I concatenate them. I am using ADS over EtherCAT protocol to transfer the files in segments to the device and then use the stand Altera flash access functions to write the file on to the flash starting from offset 0x00000000. So far this has not worked. What am i doing incorrectly here??

Cyclone IV and Nios II Firmware Update | Altera Community

24 Replies

Altera_Forum
Honored Contributor
14 years ago
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If I am comparing the flash contents, its all a bunch of ones and zeroes.. How do I know, what exactly went wrong??
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There are some tools that can be used to compare flash files. IIRC the "verify" option in the Quartus programmer will just tell you "failed" if there is a difference, without telling you more information. But if you read back the flash contents and use a tool such as srec_cmp from the srecord package (http://srecord.sourceforge.net/) can give you more information about differences between to flash files.
Altera_Forum
Honored Contributor
14 years ago
In the default development process,the bootloader load firmware(elf) from the address just after the sof file,because the bootloader can calculate the size of sof file.The default development process can be used to develop factory image(include sof and elf file and sof file offset in EPCS is 0x0).For user image(the sof and elf file offset in EPCS is user defined) you can use the bootlaoder generated by programe which download from the alterawiki.

In default development process, the"--after" option can make the flash file generated from elf have an offset in EPCS, the offset is the size of sof file. flash file contain the address infomation in it's formate.
Altera_Forum
Honored Contributor
14 years ago
@kosh271 -- Actually i am using the After tag.. Since I am not getting the desired results with that.. I am thinking of not using it in my next attempt. My hardware and software flash files have been concatenated to become a single .bin file.. So the software data is obviously after the hardware file.. So I dont how the after tag makes sense here..

and the link you provided does not actually explain the same problem.. I am not using the NIOS2 flash programmer at all.. My Flash files find their way to the Flash using a fieldbus protocol. Do you have any links that explain this process?? or Methods to boot and update firmware without using the JTAG connection...
Altera_Forum
Honored Contributor
14 years ago
If you still have not successfully booted your software from flash, I highly recommend you use the --after tag. Is there a specific reason why you aren't using it?

You might want to check out http://www.alteraforum.com/forum/showthread.php?t=27981 (http://www.alteraforum.com/forum/showthread.php?t=27981). This thread has someone fighting to get the same sort of setup you are hoping for.
Altera_Forum
Honored Contributor
14 years ago
Yes.. Except for some very very minor differences, I cant see any big difference... There is no change in the Endianness.. I mean, the nios flash programmer and the method I use both write in the data is the same order.. So that means there is no general error.. I am going to try the process without using the after tag command.. and see what happens.. But here is the thing.. If I am comparing the flash contents, its all a bunch of ones and zeroes.. How do I know, what exactly went wrong??
Altera_Forum
Honored Contributor
14 years ago
It depends on the format of the flash files. If you generate an srec (the default with elf2flash) or an hex files, they contain both the data and the address it should be written to in the flash. The --after option just ensures elf2flash starts the address just after the FPGA image. If you convert those to binary files before you concatenate them I don't believe the --after option makes any difference.
Did you try to read back the flash contents and compare with what the Nios II programmer writes?
Altera_Forum
Honored Contributor
14 years ago
Thank you very much for all your replies. I have tried the default method (using the default EPCS bootloader).. But it seems after reset, the hardware is booting up properly but the software does not run. At this point i want to ask a question regarding the "--after" tag in the elf2flash command. Do i really need to use it, even when I concatenate both hardware and software firmware in to one file before downloading. It makes sense with the Nios2-flash-programmer, since the files are being written seperately.. Do i really need it if I am going to have only one file??
Altera_Forum
Honored Contributor
14 years ago
Read the first page,you'll find how to modify the boot address,not use the default offset 0x0. The second page tell you how to use script to write the sof and elf file to the special address.
http://www.alterawiki.com/wiki/epcs_bootloaders

http://www.alteraforum.com.cn/showtopic-2692.aspx
Altera_Forum
Honored Contributor
14 years ago
It looks okay. When you use elf2flash, don't forget the --after option to place the new contents at the correct address in the flash, just after the FPGA image. The only issues I could think of are endianes or bit order. Could you read back the flash contents in both cases (when you flash with your method and when you flash with the Quartus programmer) and see if you can find any difference?
Altera_Forum
Honored Contributor
14 years ago
Thank you for the reply.

Regarding my firmware files, here is how I prepare them:
1. I use the Nios II Command shell, to generate the hardware and software firmware files using sof2flash and elf2flash.

2. Then I comvert them in to the .bin files.

3. Finally I concatenate them.

I am using ADS over EtherCAT protocol to transfer the files in segments to the device and then use the stand Altera flash access functions to write the file on to the flash starting from offset 0x00000000.

So far this has not worked. What am i doing incorrectly here??

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Cyclone IV and Nios II Firmware Update

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