Cyclone IV - timing problem with I/O pins sharing Vref

As a bit of background, here is what I am trying to do.

I have a fairly simple synthesizer design hosted on an EP4CE15E22C7N (EQFP), which is driving an AD9744 parallel load DAC. The design is supposed to operate at 100MHz. Architecturally, the DAC and FPGA share a common clock, which is split and fed to both devices. The board designer serpentined the clock traces until they are almost identical - down to literally a couple of mils delta. He was thinking that it would be possible to drive the data from the FPGA to the DAC as if they were fully synchronous. I'm not clear if that was a good idea or not, but at least on the scope, they are right on top of each other.

I have tried to constrain the I/O to the DAC using the SDC file with a set_output_delay command. I did assume the board clock skew was close enough to ignore, calculated an estimate of the trace skew at ~600ps (these are surface traces on FR4, and are about 300-340 mils in length). Tsu on the DAC is 2ns, Th is 1.5ns. In theory, I should have plenty of time to get between the two parts.

set_output_delay -add_delay -clock [get_clocks {Master_Oscillator}] -max 2.600 [get_ports {DAC_Data

[*]}]

set_output_delay -add_delay -clock [get_clocks {Master_Oscillator}] -min -0.900 [get_ports {DAC_Data

[*]}]

When I checked, the failing pins are always the same 4 out of the 14. On closer inspection, they have an alternate Vref function, which I'm assuming is contributing to the larger data delay.

Two questions:

1) did I calculate the set_output_delay command correctly, and

2) Is there anything short of using a slower sample clock I can do to fix this if so?

I am not off by much:

-0.382 Composite_Out_q[9] DAC_Data[9] Master_Oscillator Master_Oscillator 10.000 -2.462 5.300

-0.373 Composite_Out_q[3] DAC_Data[3] Master_Oscillator Master_Oscillator 10.000 -2.453 5.300

-0.369 Composite_Out_q[13] DAC_Data[13] Master_Oscillator Master_Oscillator 10.000 -2.449 5.300

-0.356 Composite_Out_q[2] DAC_Data[2] Master_Oscillator Master_Oscillator 10.000 -2.436 5.300

vs

1.614 Composite_Out_q[8] DAC_Data[8] Master_Oscillator Master_Oscillator 10.000 -2.462 3.304

1.614 Composite_Out_q[7] DAC_Data[7] Master_Oscillator Master_Oscillator 10.000 -2.462 3.304

Thanks!

-Seth