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Altera_Forum
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11 years ago

Cyclone IV - timing problem with I/O pins sharing Vref

As a bit of background, here is what I am trying to do. I have a fairly simple synthesizer design hosted on an EP4CE15E22C7N (EQFP), which is driving an AD9744 parallel load DAC. The design is ...
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Altera_Forum
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11 years ago

Hi Seth,

The timing difference of the VREF pins is warned about in the newer handbooks.

I stumbled across this timing issue a while back and created an example design. Take a look at post# 7 in this thread

http://www.alteraforum.com/forum/showthread.php?t=31457

The PDF in that post shows the results of a timing analysis, and shows how the VREF pins are the source of an extra delay.

The VREF pins have additional capacitance on them.

This doesn't really help you solve your problem, but at least it confirms you will see a timing difference when using VREF pins.

Cheers,

Dave