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Altera_Forum
Honored Contributor
11 years agoCyclone IV - timing problem with I/O pins sharing Vref
As a bit of background, here is what I am trying to do. I have a fairly simple synthesizer design hosted on an EP4CE15E22C7N (EQFP), which is driving an AD9744 parallel load DAC. The design is ...
Altera_Forum
Honored Contributor
11 years agoI think in this case it may be better to punt, and just choose a slower oscillator. Unfortunately, this means physically replacing a part, but we are well over the "minimum" sampling frequency to get adequate results from the synthesizer. The previous incarnation was running fine with a 66MHz sample frequency. Since we have no specific requirement for anything above that, it seems rather pointless to keep fighting the hardware.
On the bright side, this does explain the weird signals I was seeing on my scope. The sign bit (bit 13) is one of the bits affected, and there is at least one other high-order bit (9) with the same problem.