Cyclone IV - timing problem with I/O pins sharing Vref

I believe your figure for min should be -2.1 ns. The max of 2.6 ns is ok. The idea is that no data transition should occur between max and min but is allowed between min and max within the 10 ns clock period.

This leaves 5.3 ns margin. Even tougher than you already have. I suggest you then look for best timing window for fitter to pass. I mean try sliding the 5.3 ns window across until timing passes (through sdc) and once found then apply a PLL to phase shift your fpga clock to get a match for your figures. You may set those failing pins to different figures. Also make sure you set your outputs to use io registers.