Cyclone IV - LVTTL causing FPGA to reset

Question

I am using a Cyclone IV FPGA with a Nios Core. I have 22x LVTTL PIO defined to remain tristate and drive low when active. The VCCIO of the bank on the FPGA is tied to +3.3V.

This PIO is connected to a solid state relay cathode though a 1.91K ohm resistor and the anode is tied to +5V.

I have two of the PIO operating as normally. Many of the others, when the PIO goes low, the FPGA reboots. I have been in contact with support, case/thread 06107028 and it has been determined that my configurations are all in-order. They suggested I post something here for futher support.

farabi · Answer

Hello, please reply our request in email. regards,Farabi

aqidayman_altera · Answer

Hi,​I have taken a look at your schematic that shows the connection between the GPIO and the solid-state relay. So far, there is no difference between all the connection, so it is kind of strange why there is working one and failed one whenever the GPIO give the output low.How about the parameter settings of the PIO? Are there any differences?

michael-c · Answer

All of those PIO are set the same and use the same type of logic. They are normally set to a 'Z' or tristate. When they need to be active, they are set to a '0'.

Remembering the implemented design:

1. The VCCIO bank of the FPGA is tied to 3.3V.

2. Assuming 1.2V forward voltage drop of the solid state relay:

2.1 with the 330 ohm resistor that is approx 11mA of current into the PIO.

2.2 with 1.9K ohm resistor that is approx 2mA of current into the PIO.

A few questions come up:

1. Why does the FPGA restart when it tries to drive low?

2. Is the 11mA too much current for the device to handle?

2.1. If the 11mA is too much, could it have damaged the device?

2.1.1 Would the damage be localized to the PIO or the entire bank?

fvm · Answer

11 mA doesn't overload MAX10 IO. It's however no good design to connect anodes to 5V, IO voltage in off state potentially exceeds maximum ratings.

Curiously, both threads don't consider the possibility that solid state relay output switching causes the reported effects.

michael-c · Answer

Its a Cyclone IV device.The solid state relay in-essence is a forward bias LED with approx 1.2V forward voltage drop which is not an indictive load.I have used this design on many other boards using different Altera FPGAs and CPLDs with the same solid state relay. None of them have operated in this fashion. The only difference in this design is the +5V to the anode as opposed to +3.3V. Will the +5V on the GPIO with it in tri-state mode damage the device?What will cause the FPGA to reboot itselt?

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Cyclone IV - LVTTL causing FPGA to reset

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