Forum Discussion

Michael-C's avatar
Michael-C
Icon for New Contributor rankNew Contributor
2 years ago

Cyclone IV - LVTTL causing FPGA to reset

I am using a Cyclone IV FPGA with a Nios Core. I have 22x LVTTL PIO defined to remain tristate and drive low when active. The VCCIO of the bank on the FPGA is tied to +3.3V. This PIO is connected to...
Generic Io
AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

When you mentioned the FPGA reboot, you meant the NIOS II getting reboot only and not the whole FPGA including the I/O right?


Have you check the scope shot from the waveform of the output switching whether it has a smooth transition or a lot of spikes coming in?


Also, which two PIO that you said it is working normally?