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Michael-C's avatar
Michael-C
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2 years ago

Cyclone IV - LVTTL causing FPGA to reset

I am using a Cyclone IV FPGA with a Nios Core. I have 22x LVTTL PIO defined to remain tristate and drive low when active. The VCCIO of the bank on the FPGA is tied to +3.3V. This PIO is connected to...
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AqidAyman_Altera's avatar
AqidAyman_Altera
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2 years ago

As we do not receive any response from you, this thread will be transitioned to community support.


  • Michael-C's avatar
    Michael-C
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    2 years ago

    I'm not sure how to distinguish between FPGA vs Nios Reboot. When I enable one of the effected PIO, the embedded program re-starts from the beginning. The program has been loaded into the local EEPROM, which is what runs upon startup.

    I have monitored the power lines with an oscilloscope to see if there are any dips from the power supply (voltage regulators, etc), and there is none.

    I don't recall which of the PIO are operating properly, other than two of all of them.