Cyclone IV - LVTTL causing FPGA to reset

All of those PIO are set the same and use the same type of logic. They are normally set to a 'Z' or tristate. When they need to be active, they are set to a '0'.

Remembering the implemented design:

1. The VCCIO bank of the FPGA is tied to 3.3V.

2. Assuming 1.2V forward voltage drop of the solid state relay:

2.1 with the 330 ohm resistor that is approx 11mA of current into the PIO.

2.2 with 1.9K ohm resistor that is approx 2mA of current into the PIO.

A few questions come up:

1. Why does the FPGA restart when it tries to drive low?

2. Is the 11mA too much current for the device to handle?

2.1. If the 11mA is too much, could it have damaged the device?

2.1.1 Would the damage be localized to the PIO or the entire bank?