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Regarding the pull-ups on the EPCS interface, i looked the schematic on CYCLONE iii device handbook
"Figure 9–30. Programming Serial Configuration Devices In-System Using the JTAG Interface" P217:
and there are no pull-up or pull-down.
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Do not take figures in the handbook as an implementation recommendation, think of them more as a general guide. You need to read the data sheet for the EPCS device, and look in the handbook for comments regarding pull-ups on the configuration pins. You can also look at schematics of Altera evaluation boards. Keep in mind that a weak pull-up might be too weak, and that you should have an external pull-up. Its also easy to have an external pull-up on say chip-select and then not load it. Also check for signals that get tri-stated, eg., the data pins. You do not want those pins to float, so again, you need to see if there are weak pull-ups/downs or bus hold features on the devices, or whether you need external resistors.
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Just another question: To load a configuration into the EPCS4,
- i have to load the configuration in the first time in the FPGA with JTAG connection and .SOF file (with a SFL megafunction
and "noe_in" to "0")
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You've mixed up your configuration schemes. The JTAG header does not need nCE in JTAG mode. You only need that pin on the header if the EPCS pins connect to both an AS header and to the FPGA. In that case you deassert nCE to tri-state the FPGA drivers. Your design uses JTAG mode only, so you do not need the nCE connection from the header. Connecting nCE to ground would be fine (though there is no problem using a resistor too).
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- Then i convert SOF file in .JIC file (JTAG indirect configuration) with quartus
- I send this file with JTAG connection to the EPCS4 through CYCLONE iii (SFL bridge).
Finally my FPGA can run and configure himself automatically at the power-up.
Is-it exact?
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Yes, that is correct. If I recall correctly, the DE0-nano user manual has a nice description of using SFL to program the EPCS device on that board.
Cheers,
Dave
Honored Contributor
