CYCLONE III with AS and JTAG (SFL)

yes, there was one issue, thanks!!! i changed the MSEL pull-ups to VCCA.

Regarding the pull-ups on the EPCS interface, i looked the schematic on CYCLONE iii device handbook

"Figure 9–30. Programming Serial Configuration Devices In-System Using the JTAG Interface" P217:

and there are no pull-up or pull-down.

I put of course a couple of decoupling capacitances.

Just another question: To load a configuration into the EPCS4,

- i have to load the configuration in the first time in the FPGA with JTAG connection and .SOF file (with a SFL megafunction

and "noe_in" to "0")

- Then i convert SOF file in .JIC file (JTAG indirect configuration) with quartus

- I send this file with JTAG connection to the EPCS4 through CYCLONE iii (SFL bridge).

Finally my FPGA can run and configure himself automatically at the power-up.

Is-it exact?

Thank for your reply.