Honored Contributor
Honored ContributorHi,
Why I asked this is because there is a fine print at the bottom of table 7-2 of C3 Handbook...it says "User I/O pins are used as inputs or outputs; clock input pins are used as inputs only; clock output pins are used as output only" I think it is ONLY refering to differential I/O only... There is no "dedicated clock output" in table 1-9 (C3 datasheet) but there is "delicated LVDS output". Are you referring to this? But PLLx_clock_output is located at bank 3 4 7 8, or top/bottom....and not left/right... --- Quote Start --- I think, both questions are clearly answered in the device handbook respectively pinout tables. The pinout table clarifies, that PLLx_CLKOUT is an optional function of particular regular IO pins. (The basic function is indicated in the column Pin Name/Function). So any of these pins can be used for regular IO, if not required as dedicated clock output. Regarding pin capacitances, Table 1-9 in Cyclone III Device Handbook lists the standard and special pins capacitances. The said dedicated clock output pins are obviuosly belonging to the category I/O pin. This isn't surprizing because they are regular I/O pins. Their optional function doesn't involve changes to the I/O cell itself rather than input connectivity only. --- Quote End ---
