Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Cyclone III user I/O stay LOW during JTAG configration

Hi,all I found all user I/Os became LOW during JTAG configruation in my situation. The device is Cyclone III 3C35. However, it is said that user I/Os must be tri-stated during JTAG configuration i...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

But I still doubt why other dual purpose pins , such as DCLK, DATA0 and Flash_nCE, are tri-stated during JTAG configuration , and only ASDO pin is pull down.

In my project, the ASDO pin acts as an output request signal, which is active low. External hardware treat it as a request as soon as the pin become low. So wrong response would be caused if the pin become low during configuration. I am afraid that I must choose another pin instead of ASDO.

Regards,

hustzq