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Honored Contributor
Honored ContributorCyclone III stuck at POR?
Hi,
I have problems to get a custom board work, the FPGA seems to be stuck in POR. It's a PCIe card with a EP3C10F256C7N. I attached an excerpt of the schematic to this post. I have 10 prototype boards, they all show the same problem: nSTATUS is at LOW level and we can't test the boards with JTAG. It's our the second design with a Cyclone III, the first one worked well. I checked the power supplies, they are well inside the limits. VCCINT is 1.196V, VCCA is 2.497V and VCCIO is 3,282V. I tried to vary VCCA and VCCIO some 0.1V up and down, but without success. VCCIO is sourced directly from the 3.3V of PCIe connector, VCCINT and VCCA are made from this 3.3V with linear regulators. All VCCIO are tied together to the same 3.3V power supply. MSEL[2:0] is set to 010, that should be AS standard POR with 3.3V configuration voltage. I measured the config and JTAG pins: nCONFIG: 3.3V nSTATUS: 0V CONF_DONE: 0V nCEO: 0.2V (open?) DCLK: 3.3V nCE: 0.9V (?) nCSO: 3.3V ASDO: 3.3V DATA[0]: 3.3V TDO: 3.3V TDI: 3.3V TMS: 3.3V TCK: 0V Can nCE or any other config pin hold the device in POR? The design has migration parts (EP3C5, EP3C16 and EP3C25), therefore I have more VCC and GND pins than required for the EP3C10 connected to the device. I checked all dedicated pins (configuration and power) against a Quartus II 10.1 generated pin list. I compared it with our schematic and with the PCB artwork, but I can't find any mistake. I didn't check all of the I/O connected to the board, but all peripheral devices are powered from 3.3V, so I assume that they're within the I/O limits. Where is the mistake? What other reason can hold the device in POR? Regards, Jürgen35 Replies
Altera_ForumI think, only nCONFIG=low and a missing supply voltage (from those that are monitored) can hold the device in Reset. You didn't explicitely tell, but I assume that the device also isn't recognized at the JTAG interface?
P.S.: The FPGA pinning, as shown in the schematic is correct. Using linear voltage regulators powered from 3.3V for 1.2 and 2.5V guarantees a correct power-up sequence. I assume, that some optional resistors at the configuration interface aren't populated (e.g. nCONFIG pull-down), otherwise, the above reported measurements won't be plausible. A small detail, that I don't undertand is L3 at the EPCS supply pins without any bypass capacitors.- Altera_Forum
Also probe your power supplies to make sure they power sequence within the recommended time.
Cheers, Dave - Altera_Forum--- Quote Start --- I shortened nCE to GND, but nSTATUS is still LOW. I understand that a faulty nCE can inhibit configuring the device. But can it really hold the device in POR and inhibit JTAG? --- Quote End --- I don't know. I don't have time right now to look again in detail at your configuration circuit. However, if you wanted to, compare it to this stratix ii design, see p51: http://www.ovro.caltech.edu/~dwh/carma_board/gda06rb004_carma_v0.87_dec03.pdf Perhaps a difference will stand out to you. Cheers, Dave
- Altera_Forum
Hello Dave,
thank you for your reply. I shortened nCE to GND, but nSTATUS is still LOW. I understand that a faulty nCE can inhibit configuring the device. But can it really hold the device in POR and inhibit JTAG? Regards, Jürgen - Altera_Forum
nCE needs to be low before a device can be configured.
Try shorting the pin to ground, or figuring out why it is not 0V with the 10K pull-down. Cheers, Dave
