Cyclone III stuck at POR?

I think, only nCONFIG=low and a missing supply voltage (from those that are monitored) can hold the device in Reset. You didn't explicitely tell, but I assume that the device also isn't recognized at the JTAG interface?

P.S.: The FPGA pinning, as shown in the schematic is correct. Using linear voltage regulators powered from 3.3V for 1.2 and 2.5V guarantees a correct power-up sequence.

I assume, that some optional resistors at the configuration interface aren't populated (e.g. nCONFIG pull-down), otherwise, the above reported measurements won't be plausible. A small detail, that I don't undertand is L3 at the EPCS supply pins without any bypass capacitors.