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Vic3Dexe's avatar
Vic3Dexe
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
Solved

Cyclone III slave (PS) embedded memory errors

I have two Cyc III devices (master-slave, AS and PS respectively) + EPCS16 flash. In both devices I have ROMs (megafunction), one in the master and two of them in the slave. All ROMs are initialize...
  • Vic3Dexe's avatar
    Vic3Dexe
    3 years ago

    I think I've found the problem.

    There is a trace connected to pin 76 on the master and pin 99 on the slave. Trace is pulled up to 3.3V via 2.2k

    This **bleep** resistor was dead, and the trace was actually floating.

    I didn't use this pins before, so I can't reveal the resistor is dead.

    As I start to use it, all logic became a total mess. Something worked, something not. By elimination I found the culprit.

    I can't explain how this trace connected with loading errors (when FPGA not even in user mode), but the fact is - replacing resistor solved all problems, ROMs working now (though I don't use them anymore).

    Thanks to all, problem solved!

hareesh's avatar
hareesh
Icon for Frequent Contributor rankFrequent Contributor
3 years ago

@Vic3Dexe wrote: I've cut traces and placed series resistors afters buffers (51R)

those resistors where are you connecting (data line or clk line or on both lines)

  • if you see bellow attachment in schematic on clk and data lines using two different resistors in series.
Vic3Dexe's avatar
Vic3Dexe
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
@hareesh wrote:

@Vic3Dexe wrote: I've cut traces and placed series resistors afters buffers (51R)

those resistors where are you connecting (data line or clk line or on both lines)

  • if you see bellow attachment in schematic on clk and data lines using two different resistors in series.

As I said in post 4:

I've tried to remove buffers and change them to zero Ohm resistors - no changes.

Then I've replaced 0R resistors to 51R ones - no changes.

Then I've put buffers back, cut traces afters them (which are facing to the slave), and put 51R there in series. No changes.

So now it's like that. Both resistors placed as close as possible to buffers.

There is no point in resistors before buffers, as the master working ok.