Forum Discussion
Cyclone III slave (PS) embedded memory errors
- 3 years ago
I think I've found the problem.
There is a trace connected to pin 76 on the master and pin 99 on the slave. Trace is pulled up to 3.3V via 2.2k
This **bleep** resistor was dead, and the trace was actually floating.
I didn't use this pins before, so I can't reveal the resistor is dead.
As I start to use it, all logic became a total mess. Something worked, something not. By elimination I found the culprit.
I can't explain how this trace connected with loading errors (when FPGA not even in user mode), but the fact is - replacing resistor solved all problems, ROMs working now (though I don't use them anymore).
Thanks to all, problem solved!
There is the ROM1 content in the slave after power up:
Then I do "Import data from the file" and use the same .mif file used for ROM init:
Red numbers shows the differences. Then "Write data to in-system memory", read it back again, and "Import data from file" again:
As you can see, all numbers which were red, now are consistent with actual .mif file.
Hi Vic3Dexe,
can you please provide total procedure you are following (bit file generation, bit file loading, loads from EPCS, etc..)
- Vic3Dexe4 years ago
Occasional Contributor
1. MIF files were generated only once. I don't change them. They are constant. It's irrelevant how they are maked, because they don't change.
2. I have 2 projects in Quartus (13 sp1 web version) - one for master, and one for slave.
3. In both projects I've created "ROM 1-port" megafunctions (1 for master, and 2 of them for slave) and set according .mif files as init values. Like this:
4. Compiled (or fully recompiled) both projects, so the result is two .sof files.
5. Used convert programming file tool to create .pof file:
6. Used programmer to write EPCS:
Here is the quartus log (one of the million attemp to get it to work). Verification also always passes (if enabled).
Info (209060): Started Programmer operation at Tue Jun 21 17:23:18 2022 Info (209018): Device 1 silicon ID is 0x14 Info (209044): Erasing ASP configuration device(s) Info (209024): Programming device 1 Info (209018): Device 1 silicon ID is 0x14 Info (209011): Successfully performed operation(s) Info (209061): Ended Programmer operation at Tue Jun 21 17:25:47 20227. Power up/reset the board. Both devices loads its content from EPCS.
8. Nothing works because of broken ROMs content in the slave (and ONLY in the slave). Look at the previous post, I've described there how to detect those errors.
9. Reload the slave .sof via JTAG. Or both master and slave. No changes, ROM still has errors.
10. Reload ROMs via ISCME. No errors.
I want to empasis the problem - .mif files used for ROM initialization in project don't get in ROMs intact. And this problem exists only for slave.
- hareesh4 years ago
Frequent Contributor
hi
can you please share your platform design and files.
thanks.
- Vic3Dexe4 years ago
Occasional Contributor
What exactly files do you need?
1. Board schematics and layout? (Altium 15)
2. Gerbers?
3. Verilog files?
4. Sof/pof?
5. Mif?
6. Sources for .mif files? (x86 asm)
Where I should send them? Some e-mail maybe?