Cyclone III programming problem (JTAG and AS)

What's the actual MSEL configuration?

How did you connect the JTAG interface(s)?

Thanks for replay, FvM.

Actual MSEL configurations are Active Parallel (3.3V) for Master and Fast Passive Parallel Fast (3.3V) for next 4 slaves. Which was good for previous revision with parallel configuration. JTAG is configured in chain, as I mention before, Figure 9-26 in Chapter 9, Cyclone III Device Handbook, Vol 1. And, it sims to be JTAG is working. Autodetect in programmer showing a correct configuration and I'm able to configure the serial configuration device (EPCS64) by JTAG, as well as by AS Interface.

The board is high density 16 layers board, as well as very expencive and I would like to debug other circuits on the board before next revision, what I can't do without programmed FPGAs. So, I will really appresiate for any help and ready to submit any information which can help.

Hello,

I have built a board which has an Altera cyclone IV device (EP4CE10E22C8N). I want to configure FPGA using FTDI (FT2232HL) in JTAG mode. I am having difficulty as my board is not getting detected.

I am using UrJTAG to communicate with the Cyclone IV device. And EPCS4 as the serial memory.

An error is seen when I hit the detect command in UrJtag i.e. tdo seems to be stuck at 0

All the necessary connection as mentioned in Altera Cyclone IV datasheet.

Please let me know if u have any idea where and what am I doing wrong.

Regards,

Saurabh

hello

i am also using cyclone IV device and i am trying to configure my FPGA in jtag mode.

i am using FT2232HL for USB to JTAG protocol conversion.

but when i try to detect my device in UrJTAG console i an receiving a Warning saying

TDO seems to be stuck a 0.

i have checked all my connections 10 times, they all are as per the cyclone IV design guide and Pin connection guidelines provided by altera.

to be more specific here are the connection I made for the jtag mode of configurations.

Altera devices use the four JTAG pins for JTAG programming or configuration. They should be connected as below:

1. TCK (Test Clock) - From download cable in parallel to every device in the JTAG chain. Weakly pulled-down to GND. Check the Configuration Handbook or specific device Handbook for resistor values.

2. TMS (Test Mode Select) - From download cable in parallel to every device in the JTAG chain. Weakly pulled-up to VCCIO. Check the Configuration Handbook or specific device Handbook for resistor values.

3. TDO (Test Data Out) - The TDO pin of a device is connected to the TDI pin of the subsequent device in the JTAG chain. For the last device in the JTAG chain, the TDO pin is connected to the TDO pin of the download cable.

4. TDI (Test Data In) - TDI pin of a device is connected to the TDO pin of the preceding device in the JTAG chain. For the first device in the JTAG chain, the TDI pin is connected to the TDI pin of the download cable.

Even though other programming or configuration pins (for FPGA) are not used in JTAG mode, they must be properly connected and cannot be left floating.

1. nTRST - Driven high during JTAG configuration.

2. nCE - Connect to GND or driven low during JTAG configuration.

3. MSEL pins - Connect to ground.

4. nCONFIG - Driven high or pulled to VCC through a pull-up resistor.

5. DCLK - Either pull-up or pull-down through resistor.

6. DATA pin(s) - Either pull-up or pull-down through resistor.

7. nSTATUS - Pull to VCC through a pull-up resistor. When the device is powered-up, this pin will be released to high.

8. CONF_DONE - Pull to VCC through a pull-up resistor. Should be pulled-up individually for the devices in a chain. When the device is successfully configured, this pin will be released to high.

9. INIT_DONE - When used, pull-up to VCC.

i have also give the path for the bsdl file in UrJTAG shell.

i am not able to figure out what is the problem and why is my FPGA not getting detected.

please let me know if you have any idea as yours design seems to work with cpld and fpga.

Regards

Saurabh Agrawal

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please let me know if you have any idea as yours design seems to work with cpld and fpga.

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You can try resetting the JTAG chain and the toggle TCK and assert TMS to bring the JTAG TAP into the Shift-DR sequence. The default contents of the DR register are the device ID code. Toggle TCK 32 times, and probe TDO. It should toggle - on all device outputs.

Cheers,

Dave

Thanks for the quick response..

please can you elaborate a little more..

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please can you elaborate a little more..

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The JTAG TAP machine is on page 10

http://www.altera.com/literature/ug/ug_virtualjtag.pdf

If you hold TMS high and clock TCK 5 times, then you will end up in the TAP reset state (TEST_LOGIC_RESET). The device IDCODE will be loaded into the DR register.

If you clock in the TMS code 0, 1, 0, 0, you will be in the SHIFT_DR state.

Hold TMS low and pulse TCK for 32 clocks and IDCODE will be shifted out on the TDO pin.

Put the TAP back in reset, and repeat.

You should then have a data stream on every TDO pin on your board.

If you don't, then your JTAG chain is broken.

Cheers,

Dave

Hey,

Is there some sort of emulator or logic analyzer that is to be used for all that you suggested.

I am find a hard time figuring out that how am I suppose to this????

My PCB is ready and soldered. I have made all connections as per the altera design guide.

Why is this neccesary and do I have to repeat this for all my fpga design using cyclone 4 in jtag configuration mode.

Thanks,

Saurabh

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Is there some sort of emulator or logic analyzer that is to be used for all that you suggested.

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The Altera USB-Blaster and Parallel Port ByteBlasters can be used, a digital I/O board, a microcontroller board, etc.

Altera's Quartus tool has a JTAG debugger. It probably does the above sequence too.

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I am find a hard time figuring out that how am I suppose to this????

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Figuring stuff out like this makes you an engineer. So get to work!

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Why is this neccesary ...

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Because you said TDO was stuck at ground, and you wanted help to figure out why.

If the JTAG chain on your board works, and you can configure your device via JTAG, then of course you do not need to do any of this, since your design is working. Then you would move onto confirming that AS configuration mode works.

Don't get scared off by one failure. Its fixing the problems that is the fun part. If stuff always worked, you'd never really learn how to debug problems would you? :)

Cheers,

Dave

Hey Dave

I was just trying to find out more solutions.

and I just read that there is a grounding pad exactly at the center of the IC

which has to be ground other wise the device wont work.

but while creating the footprint of my TQFP 144 EP4CE10E22 there was not grounding pad present.

do you think this might be a reason of the device not getting detected.

And Cheers I will make it work!!! :)