Cyclone III programming problem (JTAG and AS)

Hello Dave,

I have followed these step for ccreating the svf file given by altera.

Instantiating SFL Megafunction in the Quartus II Software

Perform the following steps to generate an SFL megafunction instantiation. You must

then instantiate the SFL megafunction in your FPGA top-level design.

1. On the Tools menu, click MegaWizard Plug-In Manager. Page 1 of MegaWizard

Plug-In Manager appears.

2. Select the Create a new custom megafunction variation option and click Next.

Page 2a of the MegaWizard Plug-In Manager appears, as shown in Figure 5.

3. Select the FPGA device family from the Which device family will you be using?

pull-down list.

4. Select Serial Flash Loader from the JTAG-accessible Extensions category in the

megafunction list.

5. Select the Hardware Description Language (HDL) output file type and name the

file. Click Next (Verilog HDL was chosen for this example).

6. Specify the directory and output filename. Click Next. Page 3 of the MegaWizard

Plug-In Manager appears,

7. Turn on the Share ASMI interface in the design check box if you must share the

ASMI interface with your design. This option provides additional control pins for

controlling the ASMI interface, as shown in Figure 7.

8. The Use enhanced mode SFL check box is turned on by default. This option

provides more flexibility for JTAG cascading environment and the usage of the

SFL with a third-party programmer tool. Turn off the Use enhanced mode SFL

check box if you do not wish to use enhanced SFL.

9. Click Next until you reach the summary page.

10. Click Finish to generate the SFL megafunction. The Quartus II software generates

the megafunction in the form of the HDL file you specified.

Converting .sof to .jic Files in the Quartus II Software

To convert a .sof to a .jic file, perform the following steps:

1. On the File menu, select Convert Programming Files.

2. In the Convert Programming Files dialog box, select JTAG Indirect

Configuration File (.jic) from the Programming file type drop down menu.

3. In the Configuration device field, specify the targeted serial configuration device.

4. In the File name field, browse to the target directory and specify an output file

name.

5. Highlight the SOF Data in the Input files to convert window

6. Click Add File.

7. Select the .sof file that you want to convert to a .jic file.

8. Click OK.

9. Highlight FlashLoader and click Add Device

10. Click OK. The Select Devices dialog box appears.

11. Select the targeted FPGA that you are using to program the serial configuration

device

12. Click OK. The Convert Programming Files dialog box appears

13. Click Generate.

To convert a .jic to a .jam file in the Quartus II software, perform the following steps:

1. On the Tools menu, select Programmer.

2. Click Add File. The Select Programming File dialog box appears.

3. Browse to the .jic file you created in “Converting .sof to .jic Files in the Quartus II

Software” on page 10. Add more .jic files if you are programming multiple serial

configuration devices.

4. Click Open.

5. Select Create/Update. In the File menu, scroll to Create JAM, SVF, or ISC File

(refer to Figure 12).

6. The Create JAM, SVF, or ISC File dialog box appears

7. Click OK.

the only difference is that i have not create .jam file but .svf file.

but when i load the .svf file on to the board i get an error.

UrJTAG 0.10# 1502

Copyright (C) 2002, 2003 ETC s.r.o.

Copyright (C) 2007, 2008, 2009 Kolja Waschk and the respective authors

UrJTAG is free software, covered by the GNU General Public License, and you are

welcome to change it and/or distribute copies of it under certain conditions.

There is absolutely no warranty for UrJTAG.

WARNING: UrJTAG may damage your hardware!

Type "quit" to exit, "help" for help.

jtag> cable ft2232

Connected to libftd2xx driver.

jtag> detect

IR length: 10

Chain length: 1

Device Id: 00000010000011110001000011011101 (0x00000000020F10DD)

Manufacturer: Altera

Part(0): EP4CE10

Stepping: 1

Filename: d:\urjtag\data/altera/ep4ce10/ep4ce10

jtag> svf c:\test\fulladd.svf

warning svf: unimplemented mode 'absent' for trst

error svf: sir command length inconsistent.

in input file between line 34 col 1 and line 34 col 20

error occurred for svf command sir.

please let me know what and where i am doing it wrong.

THANKS

Saurabh