Cyclone III pin configuration

EPCS can be perfectly programmed through indirect JTAG, if you don't mind to convert the programming files. So the AS connector can be saved. MSEL would be pinstrapped to AS normally.

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Aside from these pins, the VCCIO, VCCINT, and GND pins, are there any other pins that have to be correctly configured for the FPGA to be programmed and run properly? The PLL pins are not necessary, correct?

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The configuration related signals, particularly NCONFIG and NSTATUS must be wired with pull-up resistors according to the hardware handbook. PLL supply pins must be connected to VCCA, even if the respective PLL is unused. Not exactly a pin, but it's important to connect the exposed pad of E144 package to GND.

The EPCS devices do not support JTAG and you can't use the same pin header for JTAG and EPCS AS programming.

That said, Altera did not go dumb and you don't need to have two pin headers.

You can still program the EPCS via JTAG using JTAG Indirect Programming. First, the FPGA is loaded with a Serial Flash Loader configuration. Then, the EPCS is programmed from JTAG through the FPGA.

Thus, you only need to have pin headers for JTAG.

Yes, MSEL must be set for AS.

Go to http://www.altera.com/literature/lit-cyc3.jsp and check your design against the guidelines.

In particular, double check against the Device Pin Connection Guidelines. There's a lot of more pins that you may or may not have to worry about, depending on your I/Os (VREFs, RDNs, ...).

If you want to use even one PLL, you need to connect all the PLL power pins.

Even if you don't want to use PLLs, I'm not sure it's safe to leave them unconnected. Guidelines say it's not.

BTW, you'll notice that the recommended I/O voltage for JTAG in Cyclone III is 2.5V.

I think it's possible to use 3.3V as well, but if you intend to, best check here in this forum first.

Perform pin assignment and synthesize an empty top level before signing off your PCB for manufacturing to make sure your assignments don't violate any rules.

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I think it's possible to use 3.3V as well, but if you intend to, best check here in this forum first.

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For singe ended IO, CIII supports 3.3V, but its IO output buffer strength is limited to a low current 4ma drive. At 2.5&3.0V LVTTL CIII can use higher current strength settings which gives more options for higher speed IO.

Also, while the configuration programming is done, the CIII VCCIO supply for the programming pins ideally would match the IO voltage of the configuration device which can be an issue if you had planned to use the IO bank at a different IO voltage.

Also besides the the data book which has recommended hookups for the various config modes, I also found the pin out/pin list (u can downloaded off altera web site) to be good in a quick sort of way of explaining what the the programming pins are and how to decouple the PLL power pins.