Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorCyclone III max I/O frequency
Hi,
I´m using a PLL to generate a 250Mhz clock with a phase shift of 2,7ns on a CylconeIII EP3C25(-8) I want to provide this clock on a pll output pin with SSTL 2,5V standard. In quartus II Version 7.1 I got this message: Warning: Clock period specified for PLL output clock "pcixp_to_wb_top:g1x125|pxpll_altera:px_pll|altpll:altpll_component|altpll_b7q1:auto_generated|clk[2]" must be greater than or equal to 4.761 ns for output I/O "px_txclk" Is it only possible to have 210Mhz on this output pin? What can I do to solve the problem? regards cyclone12 Replies
Altera_ForumLooking at the table in the PDF noted above you'll have to know whether it is a row, column, or dedicated pin like a PLL output pin. Also, which SSTL2 Class.
- Altera_Forum
(I'm guessing that you are driving at 1.8V levels on a dedicated clock output).
Have a look at : "Maximum Output Toggle Rate on Cyclone III Devices (MHz)" in here: http://www.altera.com/literature/hb/cyc3/cyc3_ciii52001.pdf (http://www.altera.com/literature/hb/cyc3/cyc3_ciii52001.pdf) You may have to use a higher speed grade.
