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Altera_Forum's avatar
Altera_Forum
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17 years ago

cyclone iii m9ks perform not so well

i apply a design to EP3C120F484C8 noticing m9ks don't perform perfectly well at above 170 mhz, that is, at occasional address the readdata doesn't agree with what has been written.

for testing purpose, bringing down frequency to half or using stratixiii instead both escape the problem

althought device datasheet says the best performance can be up to 260 mhz, i reckon that simply refers to speed level 6.

can anyone please tell if 170 mhz or something will indeed lead to unstable use of m9ks on cycloneiii c8? thanks a lot.

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    The performance of memory block depends heavily on port registering. You must use both registered inputs and outputs to get close to the maximum performance.

    Regardless, make sure you are correctly constrainting your design. Timing analyzer should detect if your clock frequency is too high.