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Altera_Forum
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16 years ago

Cyclone III FPGA set to I/O mode

Hello all, well i am a bit new to Cyclone III FPGA, so, the problem i am having is a bit strange. i have made VHDL IP-core, which worked fine previously on my MAX-II CPLD, but now i wanted to r...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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Thanks for sharing this, but it still makes me wonder why. Any idea? Frank?

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Unfortunately not. I expected the SDRAM to be deactiveted reliably by weak pull-ups. Theer must be something special with the circuit.

The more interesting question is, if the final design will work. Good luck!

Frank