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Altera_Forum's avatar
Altera_Forum
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15 years ago

Cyclone III FPGA set to I/O mode

Hello all, well i am a bit new to Cyclone III FPGA, so, the problem i am having is a bit strange. i have made VHDL IP-core, which worked fine previously on my MAX-II CPLD, but now i wanted to r...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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It Worked :), thanks a-lot for the help.

as for your interest, i had following findings

well the output results were the same when set to "tri-state with weak pull-up" (i.e. everything still not working),

but every thing get normal when i changed it to "as input tristate with bus hold circuit" now the core is working as it should !!!

thanks,

regards.

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Thanks for sharing this, but it still makes me wonder why. Any idea? Frank?

-- Ton