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Altera_Forum
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16 years ago

Cyclone III FPGA set to I/O mode

Hello all, well i am a bit new to Cyclone III FPGA, so, the problem i am having is a bit strange. i have made VHDL IP-core, which worked fine previously on my MAX-II CPLD, but now i wanted to r...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I've never seen or heard of a wrong configuration. Or it configures, or not.

You could implement an independent counter on some unused pins and check if that one keeps running in both situations. If it is, you may assume that there's nothing wrong with the configuration.

I'm afraid I can't help you any further.

Success, Ton