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Altera_Forum
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15 years ago

Cyclone III FPGA set to I/O mode

Hello all, well i am a bit new to Cyclone III FPGA, so, the problem i am having is a bit strange. i have made VHDL IP-core, which worked fine previously on my MAX-II CPLD, but now i wanted to r...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Well, this is realy difficult to understand without knowledge of the design.

Are you telling that there are no connections inside the FPGA between the IPcore and the SDRAM pin-outs?

And that making the SDRAM pin-outs tristate or one has impact on the IPcore?