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What ist "embedded cut-path timing "?
I have configured the FIFOs so that there is no relation between the two clock domains.
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Typically the dcfifo megafunction is used to transfer data between clock domains that do not have a synchronous relationship or that do have a synchronous relationship but with a phase difference that prevents synchronous transfers. For some applications, a Classic Timing Analyzer project-wide cut-path setting is enough to prevent timing analysis of the cross-domain paths through the FIFO. Now that I think about it, this is probably what Dalon referred to, not the cuts specific to the FIFO that I had in mind. For other applications, other cut-path settings are needed, and those settings are embedded in the FIFO megafunction HDL for use by the Classic Timing Analyzer.
In the "More Timing Settings" dialog box, "Cut paths between unrelated clock domains" defaults to "On" for the Classic Timing Analyzer. That project-wide cut covers cases like the FIFO write and read clocks coming from two different clock pins on the device (whether or not a PLL is between the device input clock pin and the FIFO).
For some dcfifo applications, the Classic Timing Analyzer will by default analyze the timing between the FIFO clock domains. An example is the FIFO write and read clocks coming from two outputs of the same PLL. The Classic Timing Analyzer considers these clocks to be related to each other unless you have a cut-path setting. The dcfifo megafunction embeds the cut-path settings into its HDL for you as shown at the end of this post.
With TimeQuest, you have to add the false-path exceptions yourself. That might be as simple as false-path exceptions in both directions between write clock and read clock if you have no synchronous paths between those clock domains outside the FIFO. (The dcfifo megafunction has paths going both directions between domains. You can use set_clock_groups instead of set_false_path for this.) If cutting between clocks might cut too many paths, you can create false-path exceptions for TimeQuest similar to those embedded in the dcfifo HDL for use by the Classic Timing Analyzer.
This is discussed in the Single- and Dual-Clock FIFO Megafunction User Guide, version 4.0, Chapter 3, page 3-9:
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Setup and hold-time violations that occur on the synchronization pipeline registers (*dcfifo*dffpipe*) can be safely ignored.
In the Classic Timing Analyzer, these paths are cut by default and therefore no timing violations are reported.
However, in the TimeQuest Timing Analyzer, these paths are not cut automatically. To remove the resulting setup and hold-time violations, you must apply the Set False Path timing constraint to explicitly cut these timing paths.
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The cut-path settings I showed in my previous post are listed inside a megafunction HDL file. I did a little looking and found them for my test case. My dual-clock FIFO MegaWizard variation file instantiated the dcfifo megafunction. When that megafunction was synthesized, the dcfifo_o4e1.tdf AHDL file was created in my db directory. That file had the line shown below. The end of this line has the two cut-path settings I copied from the "Timing Analyzer Settings" table to my previous post.
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF;REMOVE_DUPLICATE_REGISTERS=OFF;suppress_da_rule_internal=d101;suppress_da_rule_internal=d102;suppress_da_rule_internal=s102;{ -from ""rdptr_g"" -to ""ws_dgrp|dffpipe7|dffe8a"" }CUT=ON;{ -from ""delayed_wrptr_g"" -to ""rs_dgwp|dffpipe4|dffe5a"" }CUT=ON";
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