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I can't tell whether you're wondering if the timing is preliminary or if you already know it and just wonder if that's related to the problem. If the former, look for a Fitter compilation message like the one below, which I got with QII 7.1 SP1.
Warning: Timing characteristics of device EP3C25E144C7 are preliminary
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Im not wonering about that message, but I want to know if that could have sth. to do with my problem
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The dual-clock FIFO megafunction has embedded cut-path timing assignments for paths going between clock domains. The Classic Timing Analyzer (not TimeQuest in QII 7.1 SP1) uses those automatic cross-domain cuts. In the Timing Analyzer compilation report, they will be listed in the "Timing Analyzer Settings" table (example below) if they were used or in the "Ignored Timing Assignments Table" if the design didn't need them.
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What ist "embedded cut-path timing "?
I have configured the FIFOs so that there is no relation between the two clock domains.
Honored Contributor
