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Altera_Forum's avatar
Altera_Forum
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15 years ago

Cyclone III EP3C25 High Temperature Booting Problem

Dear Friends,

I am facing a high temperature booting problem with EP3C25F324. I found that the FPGA can not boot up at temperature over 40 Centigrade while doing the temperature cycling tests. Once cooling down to the room temperature, the FPGA can be successfully booted up again. I have checked all the boards at hand and they all have such kind of high temperature booting problem. By the way, the FPGA can work very well in high temperature environment once booted up, even in the temperature over 60 degree. Also, I have verified that it is the FPGA itself can not boot up successfully at high temperature, not the EPCS flash, by using a cold spray foam.

Hope some body can give me a help on this issue. Thanks.

Warm Regards,

Bai Yu

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    does this mean with jtag you can figure your system and it runs fine but not via epcs ?

    can you measure the epcs configuration related signals ?

    have you connected the nCE and MSEL signals directly to GND and 2,5V or via some kind of resistor ? they need to be directly connected 0 Ohm

    the Cyclone 3 needs a smal resistor (~25 ohm) directly after the output of the epcs
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Actually I used the AS and JTAG combining configuration scheme. I have checked that all the MSEL signals are all directly connected to GND and 2.5 V respectively. But for nCE, I used a 10K ohm as the pull down resistor. This is also the suggestion from the handbook of cyclone III- Chapter 9-figure 9-29:Combining JTAG and AS Configuration Schemes. I exactly followed this scheme.

    By the way, during the test, I found that the only thing which can affect the booting process is the high temperature; in room temperature, everything goes well without any problem.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    You should be able to further trace down the configuration process. Does the EPCS read start, is it possibly aborted, because the FPGA means to detect a CRC error? What do you see at the CONF_DONE and nSTATUS pins?

    Generally I see mainly three possible causes for configuration failure:

    - FPGA isn't coming out of reset

    - wrong level of configration related pins, e.g. due to leakage currents

    - configuration data are considered invalid

    P.S.: Also a bad solder joint or broken PCB with temperature dependant behaviour may be an explanation