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Altera_Forum's avatar
Altera_Forum
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16 years ago

Cyclone III Configuration

I have developed a custom board using Cyclone III (EP3C16E144C8) FPGA. I am using JTAG for programming and debugging purpose.

I have attached the schematics for the configuration pins.

The problem I am facing currently is that while emulating the singals on Signal TAP II file, I find Reset pin to be always high. I checked the signal using a multimeter and it was low.

I am still unable to understand why FPGA is considering the input of reset pin High.

Please notify me in case if I have any wrong configuration

Thanks

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Yes, I have grounded all three MSEL[0..3] pins for JTAG configuration.

    --- Quote Start ---

    (6) Do not leave the MSEL pins floating. Connect them to VCCA or GND. These pins support the non-JTAG configuration scheme used in production.

    Altera recommends connecting the MSEL pins to GND if your device is only using the JTAG configuration.

    --- Quote End ---

    although I have also interfaced a EPCS4 in case I need to use Active serial configuration in future. (please refer to schematics attached)

    can the presence of EPCS4 hardware be an issue ?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    gotcha .. i ve to ground the pin instead of leaving it floating

    i did it and issue was solved

    thanks :D