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Altera_Forum's avatar
Altera_Forum
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13 years ago

Cyclone III configuration problem with Active Parallel flash

Hi, All,

I've trying to store mt configuration and code data in an external flash, via Active Parallel interface.

Using the Flash Programmer, I'm able to burn the .flash file to the external flash (verification is OK).

However, when I'm powering down the board and powering it back on- the configuration data is

not loaded to the FPGA.

Some (possible) helpful info:

1. After burning the flash with the config+code, if I'm using JTAG to burn the .sof- The CPU starts

running the code! That means, I think, that the code was indeed burned to the flash correctly.

2. I've checked nStatus and it's always LOW (i.e, configuration failed). Init_Done stays low all the time,

which means that the FPGA did not recive the configuration header.

So, why does the configuration fail, why the code loads correctly from the external flash?

Any ideas?

Thanks, Ran

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Update:

    After setting the --offset adress in the sof2flash to 0x2000, I'm now able to burn the configuraion data to the flash, and the FPGA reads it when

    waking up.

    However, if I burn the software data after the configuration data- the FPGA cannot read the configuration data anymore...it is as if the software

    data "runs over" the configuration data in the flash- but I can't see any way to control their locations in the flash.

    Any idea?

    Ran
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    IIRC (I'm not using parallel flash) the FPGA image must always be placed at address 0x2000 because this is where the FPGA will look for (as long as you aren't using remote upgrade). Your problem is probably as you suspect that your application code is overlapping the FPGA image, so the image is corrupted when your flash it. Fortunately you can move your application to another place in the flash. In SOPC builder/QSys you can edit the Nios CPU parameters and adjust its reset address to somewhere after the FPGA image. To find out the FPGA image size, I think the Flash programmer can generate a map file that will tell you the start and end address of everything it flashes. Alternatively you can use a tool like srec_info on the generated .flash file.

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Thanks for the reply, Daixiwen.

    I tried changing the reset address- still no good.

    I noticed in some application note a mention about 'Configuration Controller' for the FPGA. I wasn't able to understand

    exactly if it's a must or just an option. Any one knows?

    Ran
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    After you change the reset address, be sure you regenerate everything: generate the SOPC/QSys component, recompile the Quartus project, re-generate the BSP, compile it and compile your application.

    did you check with the memory map that you indeed placed the software outside the area used by the FPGA image?
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Ok, I got it after talking to Altera support.

    It seems I needed to follow the instructions written in "NIOSII Evaluation user guide, Cyclone III edition":

    http://www.altera.com/literature/ug/niosii_eval_user_guide.pdf

    Once I did the steps stated in page 69 and forward, I managed to place the configuration

    and application data both in the flash memory, and boot from the flash.

    Still, this is a mystery. There's hardly any explanations as to why those steps work.

    Altera should take note- the documentation on this feature is not good enough.

    Does anyone know of an app note or such that explains the boot process of the cyclone 3, the flash contents, etc?

    Ran