Cyclone III configuration problem with Active Parallel flash

IIRC (I'm not using parallel flash) the FPGA image must always be placed at address 0x2000 because this is where the FPGA will look for (as long as you aren't using remote upgrade). Your problem is probably as you suspect that your application code is overlapping the FPGA image, so the image is corrupted when your flash it. Fortunately you can move your application to another place in the flash. In SOPC builder/QSys you can edit the Nios CPU parameters and adjust its reset address to somewhere after the FPGA image. To find out the FPGA image size, I think the Flash programmer can generate a map file that will tell you the start and end address of everything it flashes. Alternatively you can use a tool like srec_info on the generated .flash file.