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Altera_Forum
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16 years ago

Cyclone III Clock

Hi Dear all

I am new in this forume and also FPGA projects

I want to use one of the cyclone III FPGAs in my project (EP3C80 probebly 8N) and I want to make sure what is the clock frequency input need to work with this FPGA.

I found a table in CyclonIII data sheet titled: Cyclone III Clock Tree Performance (http://www.altera.com/literature/hb/cyc3/cyc3_ciii52001.pdf page 14). is this the maximum clock frequency input that we need to connect to CLK0 to CLK15?

I previously was using another FPGA (EP1C12) which just had CLK0 to CLK3

do I need to connect all CLK0 to CLK15 pins to input clock source ?:confused:

I appreciate if you can answer my Qs!

Regards

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    do I need to connect all CLK0 to CLK15 pins to input clock source

    --- Quote End ---

    Surely not all of them. If your application probably requires multiple PLLs, you may want to provide a direct clock input to each of the four PLLs for optimal performance, e.g. CLK0,4,8,12. But Cyclone III has also an option to use a global clock source as PLL input, so if clock jitter isn't that critical, a single clock input can supply all PLLs.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Hi and thanks for your response

    as I concluded from datasheets and pin information there are 4 pins for each PLL here in cyclone III while in Cyclone 1 it was just 2 pins for that!!!

    so I want to use 2 PLLs in normal mode e.g. PLL1 and PLL2.

    for PLL1 I have CLK0..CLK3 and I will connect CLK0 and CLK1 (which are differential clocks) and for PLL2 I will connect CLK4 and CLK5 to (which are differencial clocks) and as I am not using other PLLS I will connect remaining pins to GND

    I'm wondering if anybody can let me know if I am doing wrong or right!!:confused:

    Thanks
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    The clock inputs have to be connected as differential pairs, if a differential I/O-standard, e.g. LVDS is selected. For singled ended standards as LVTTL or LVCMOS, any clock pin of a PLL can be used. But it's no problem to have extra clock inputs, so your clock setup should work in any case.