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With a Nios II processor instantiated in the FPGA you can connect to UART port on one side and you simply have the HAL driver to interface EPCS on the other side.
The other solution would be using the Freescale processor to drive the EPCS.
Both are viable: the first one would consume FPGA resources but it's easy to implement. The second one requires minimal hw resources but you'll have to write the EPCS driver for the Freescale (IIRC Altera doesn't disclose the details to program the EPCS device, so you'll possibly have to find out the commands as well).
If I had plenty of spare resources in my FPGA design and enough headroom for future upgrades, I'd definitely choose the first solution.
One remark: using a Nios processor would cause your image file to grow because it will also contain the Nios program; make sure your EPCS4 device is able to fit the 2 bigger images.
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Thanks Cris72. The FPGA design itself is relatively small, utilizing less than 20% of the resources and less than 1% of the memory bits. So I am pursuing the 1st option as you suggested. I found an example at
http://www.alterawiki.com/wiki/epcs_based_remote_system_update_(rsu)_example_on_bemicro_sdk talking about remote update EPCS using Nios II. I tried to follow it, but encountered an error when build the project "
error: file project_sources/demo_images/factory_hw.flash is absent." As a matter of fact, the whole demo_imagines folder is empty. Any idea???
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