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Altera_Forum
Honored Contributor
8 years agoAfter a year, I come back to my problem. So I still trying to get this to work.
To make it clear, I have a logic design in FPGA (no soft core etc, purely state machine and logic). Once compiled, we converted it to a .jic file and program the Cyclone III / EPCS4 at factory with JTAG interface. Once the product is shipped, we have no way to upgrade the FPGA in the field. We have an unused UART interface connected from a Freescale processor to the FPGA pins. The freescale is communicating with outside world. So my end goal is that via this UART interface, we can somehow upgrade the EPCS4 and trigger a reconfigure of the FPGA. I understand that it's better to have 2 imagines on the EPCS4 in case the upgraded one is no good, the FPGA can fallback to the factory shipped one. So question# 1) how can I realize this design? Do I need a Nios II processor?