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How much can the LCELL delay change between chips? I need to achieve some +/- 4ns delay or more so if the LCELL timings change with less than 25% i should be good.
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The timing models cover the timing range for all contributions to variation from process, voltage, and temperature. The reported timing does not distinguish between each contributor.
The "change between chips", which is in the process variation, includes the possibility that the chips will actually be as fast as the fastest speed grade even if the chips are marked with a slower speed grade. That's why TimeQuest does not include the speed grade in the name of the fast operating conditions; it uses the same fast-model timing for all speed grades. In order to minimize the variation over process, use the fastest speed grade devices so that the slow model for your speed grade will be as close as possible to the fast model.
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