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Altera_Forum
Honored Contributor
17 years agoThanks Brad. I will look into your suggestions. I have used a PLL output to phase shift some signals but i have no more PLL outputs available so i'm trying to affect I/O timings by configuring the IOEs. It appears not to work at all. I have used LCELLs in the past but since the timings may change with temperature, chip batch etc it seems unreliable.
How much can the LCELL delay change between chips? I need to achieve some +/- 4ns delay or more so if the LCELL timings change with less than 25% i should be good.