Cyclone II Configuration Basics

The app note makes it look worse than it usually is, because it's describing some of the gruesome details.

To write an EPCS through JTAG, you must first download into the FPGA a configuration which includes the SFL function.

There are two options for this:

a) you do not include the SFL in your design and download an Altera provided configuration which just implements the SFL into the FPGA whenever you want to program the EPCS

b) you include the SFL into your design

What most people do is use option "a)".

Then we just apply what's described in the "Converting .sof to .jic Files in the Quartus II Software" and "Programming Serial Configuration Devices Using the Quartus II Programmer and .jic Files" parts of the app note.

It just requires a few more clicks to generate the programming file.