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Honored Contributor
Honored ContributorCyclone II : Configuration through Embedded JTAG
Dear All, i am new to the FPGA world. I am using FPGA for signal processing. i have the *.rbf file. i want to load this file into FPGA SRAM.this the following step i m performing: ...
Altera_ForumHonored Contributor
Honored ContributorI have to correct my statement regarding JTAG configuration streams. I was thinking of the JAM player method used for PLD prgramming, however JTAG FPGA configuration is actually sendng a cotinuous binary configuration stream (LSB first), as documented in the Jrunner source code. But a 44 byte header has to be stripped before, as said.
The TDO signal during configuaration isn't specified and not checked normally, I think. Cause the TDO stream is send to the configuaration controller rather than a scan chain, I would expect that's it's delayed in PROGRAM state by one clock as in BYPASS. Watching a variable delay may actually indicate incorrect JTAG timing. The complete JTAG timing specification for Cyclone II is given in the device manual. With cyclone II,up to 25 MHz JTAG clock is possible.
