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Altera_Forum's avatar
Altera_Forum
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16 years ago

Cyclone II - IR drop debug

Hi guys

I was wondering if there is any way to validate the FPGA (Cyclone II-35 in this case) configuration after it has been working in user mode for some time.

We've got a problem happening after several hours of normal operation, the whole system goes nuts.

We suspect that occasional voltage drop caused by weak power supply might do something bad to the SRAM cells holding the configuration data and screw the internal logic, just have no way of validating it.

If we could dump the FPGA configuration data and compare it to the originally loaded rbf file, then we'll know for sure that the problem cause is power supply.

Appreciate your help on this one,

Michael

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Configuration readback isn't possible with Altera FPGA, but the error detection CRC feature available with Cyclone II gives reliable information about configuration integrity. Refer to the Cyclone II hardware manual and AN 357 detection using crc in altera fpgas.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I would expect user logic would go bad well before SRAM data. Plus, I'm pretty sure the devices have their own power detection such that if it loses enough power, it will just lose all configuration info(like a power-down), rather than sporadic bits. I've never heard of SRAM bits flipping bits or anyone worrying about this besides SEUs. I would suggest debugging the problem just like a logic problem, i.e. put in SignalTap and start pulling out signals to see what's going wrong. It's slow and painful, but usually gives the best results.