Cyclone I (EP1C3) Configuration Issues: Sequence and Environment Dependent Failures

Hi HKana17,

Thanks for the detailed write-up. With legacy Cyclone I and older Quartus, there are many possible causes here (power, flash wear, board variation, cable/driver differences, programming settings, and more). As written, it is difficult to troubleshoot because it mixes several symptoms across different boards, dates, and environments.

To keep this focused, could you please pick one failing board and one specific failure, then share only the minimum items below?

1. Which exact file is used (SOF or POF), and the full Quartus version build string
2. Programming method (JTAG or AS), and the exact Programmer settings used (including verify, erase, compression, and any “auto-detect” results)
3. The board power-up sequence and whether the FPGA is configured from EPCS at power-up or only after programming
4. What you observe on key pins if available (nSTATUS, CONF_DONE, nCONFIG), or any LEDs tied to them
5. A repeatable step list: start condition, program steps, power cycle or not, and expected vs actual behavior

Without a repeatable single-case report, the best anyone can do is guess. If you can narrow it to one board and one reproduction path, people here can give more targeted advice.

Regards,
Fakhrul