Forum Discussion
Altera_Forum
Honored Contributor
13 years agoI tried connecting the output of the ALTINT_OSC to ALTPLL's clock input but I'm getting the error below:
inclk[0] of pll must be driven by a noninverted input .... It appears to be not possible to use a PLL to generate another clock. Or am i doing something wrong? Is there a way to check if the ALTINT_OSC clock output is routed to the FPGAs clock network?