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Altera_Forum
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15 years ago

Cyclone 3 (ep3c40f84c7/c8)

cyclone 3 (ep3c40f84c7/c8)

Can You Help,

I am using an EP3C40F484C7/C8 Cyclone 3 in an Industrial Control project.

The project was written in verilog and includes spI Interfaces, sram ,

Can etc with SOPC builder nios.

the design compiles ok but fails timing analyser checks, slow timing

every time (critical error flagged up).

reqd pulse width =20.2ns high and low

actual min width = 5ns high and low

This happens also when I remove all the pin assignments.

The Classic analyzer was set to 100 MHz, all timing driven through the PLL

When changing speed grade of the device this doesn’t seem to make any

Difference to the timing errors.

Should I use classic timing analyzer and following the timing optimization advisor?

Or use Time Quest, but I am not very familiar with it.

Could this verilog code orientated?

Could it be the way I use the timiming analyser ?

thank you for you help in advance

david

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Altera has made classic timing analyzer obsolete. TimeQuest is what they only recommend now. If you only have the sopc system in your design and don't need special constraints on external i/o, migrating to TQ shouldn't be difficult: simply follow instructions in the TQ tutorial.

    If you want to keep on with classic analyzer then, yes, the advisor could help a little, at least with setting the correct compilation options.

    Anyway, IMHO the required pulse width about 20ns means that you have somewhere in the design a 25MHz or 50MHz clock besides your main 100MHz; maybe a generated signal inadvertently used to clock something?

    Cris
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi Cris,

    I have looked at your reply thanks.

    In Quartus/clocks

    I find that my main pll o/p is 100MhZ

    I have a crystal (on pcb)clock input of 50Mhz

    An altera reserved Tck of 100MHz

    We used a de1 pcb first with a cyclone 2 (50Mhz Crystal i/p).

    I dont know that met slow timing for are application,

    now we are using a cyclone 3 as mentioned

    I think the 50Mhz signal is fed into the pll

    So it doesnt appear that i will establish my timing

    because of the 50Mhz clock,Could I increase the crystal

    Mhz to say 100MHZ, but the would't it mess up the pll ?

    Thanks

    Again