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Honored Contributor
Honored Contributorcyclone 2 only support output pin up to 360MHZ?
Hi! I draw a simple PLL using altpll setting with two frequency generate which are in 100Mhz and 500Mhz. however, I found that during compiling process, there is an error saying that target dev...
Altera_ForumHonored Contributor
Honored Contributorcritical warning: output pin "da_clkp" (external output clock of pll "pll:inst|altpll:altpll_component|pll_altpll:auto_generated|pll1") uses i/o standard 3.3-v lvcmos, has current strength 2ma, output load 0pf, and output clock frequency of 90 mhz, but target device can support only maximum output clock frequency of 64 mhz for this combination of i/o standard, current strength and load;
when i compile my project ,there is the warning above,the pattern of the device is ep3c40f324,and the software is quartus ii 8.1.how can i deal with it? thank you!
