Forum Discussion
Hi,
Somehow this thread deviated from the original question:
Using 3.3V Active Serial configuration, bank 1 is bound to 3.3V as it is the configuration voltage.
Can I still use 1.5V on banks 5, 6 and 8?
The documentation is somewhat unclear if all banks containing some IO pins (1, 5, 6, and 8.)
The following experiment suggests that the configuration voltage standard (set by the MSEL pins) apply to the banks of the active configuration scheme only:
1. Create a Quartus project, selecting the target device
2. Using the pin planner, assign the desired voltage standard to each bank.
3. Using the "Device and Pin options" dialog, select the configuration scheme, configuration device IO voltage. I did also select Force VCCIO to be compatible with the configuration IO voltage.
4. Run the IO Assignment Analysis task (Compile design > Analysis & Synthesis)
In my case I selected 3.3V Active Serial, and tried selecting 1.8V to all banks (1-8). The IO assignment analysis fails, saying I cannot have 1.8V on bank 1. This makes sense, as the Active Serial IO pins use that bank.
Selecting 3.3V to bank 1 and 1.8V to the other banks, the IO assignment analysis succeeds. This take this as confirmation to my original question.
Unless this is not correct, I consider the case closed.
Regards,
Ivar Svendsen.