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- Altera_Forum
Honored Contributor
I agree that the PCI clamp POR state is apparently not mentioned anywhere in the device handbook or data sheet.
Reading that PCI clamp "should" or "must" be enabled for certain IO standards suggests that it's not enabled before user mode configuration takes effect. The same behavior is known with any other Altera FPGA providing PCI clamp diodes. In other words, they can't protect the FPGA against external signals already present during configuration phase.